Non-volatile memory (NVM) devices typically are composed of an array of bit cells, with each bit cell storing a corresponding bit of data. Each bit cell generally is configured as one or more transistors capable of storing charge, and thereby affecting the relationship between the control electrode voltage and the drain current of the transistor. The transistor is “erased” to one state (e.g., a logic “1”) by clearing the charge and the transistor is “programmed” to another state (e.g., a logic “0”) by storing charge at the transistor. Thus, the bit value “stored” by the transistor can be sensed by comparing a reference (either a current or a voltage) with the drain current of the transistor in response to the application of a read voltage to the control electrode of the transistor, whereby the “stored” value is determined to be one state (e.g., a logic “1” or an “erased” state) if the drain current is greater than the read reference and determined to be another state (e.g., a logic “0” or a “programmed” state) if the drain current is less than the read reference.
Conventional NVM architectures make use of a reference cell to generate the read reference, whereby the reference cell is similar in structure as the bit cells used to store data so as to closely mimic the characteristics of the bit cells being sensed. However, the reference current output by a reference cell typically decreases during operation. Under certain conditions, this degradation of the read reference output by the reference cell can result erroneous read and write operations. Implementations having memories in continuous or near-continuous operation are particularly susceptible to the degradation of the reference cell. Accordingly, an improved technique for implementing a reference cell for sensing bit cells of a memory device would be advantageous.
The use of the same reference symbols in different drawings indicates similar or identical items.